1. Field of the Invention
The present invention relates to a flash memory manufacturing method and particularly relates to a method of manufacturing a MOS transistor in the memory region and the peripheral circuit region of a flash memory.
2. Description of the Related Art
Conventionally, an EPROM and an EEPROM have been well known as a nonvolatile semiconductor memory device. Among those devices, attention has been particularly paid to a flash memory electrically storing all information simultaneously or in block units.
The conventional flash memory manufacturing method will be described in the order of manufacturing steps with reference to FIGS. 1 through 10. As shown in FIG. 1, an element isolation region 2 is formed by selectively oxidizing a semiconductor substrate 1, and a memory cell portion A, an nMOS region B of a peripheral circuit portion and a pMOS region C of the peripheral circuit portion are formed. Thereafter, phosphor atoms are injected into the nMOS region B of the peripheral circuit portion by selective ion implantation, while boron atoms are injected into the other regions A and C. Thermal treatment is conducted at 900.degree. C. to 1200.degree. C. to activate the injected impurity atoms, thereby forming a P well 3 and an N well 4.
Next, as shown in FIG. 2, after exposing the surface of the semiconductor substrate 1 in the element isolation region, thermal treatment is conducted to thereby form a tunnel oxide film 5-1 having a thickness of 10 to 15 nm and to form a first polycrystalline silicon film 6 and an insulation film 7 having a thickness of 100 to 250 nm only on the memory cell portion A.
Now, as shown in FIG. 3, the tunnel oxide film in the nMOS region B and pMOS region C of the peripheral circuit portion is removed and thermally oxidized. Thus, gate oxide films 5-2 and 5-3 are provided on the peripheral circuit portion and a second polycrystalline silicon film 8 is provided on the entire surface. A high melting point metal film such as tungsten and molybdenum or a high melting point metal silicide film mixed with silicon is sometimes formed on the second polycrystalline silicon film 8.
The second polycrystalline silicon film 8, the insulating film 7 and the first polycrystalline silicon film 6 on the memory cell portion A are selectively etched, thereby selectively forming a floating gate electrode 6 and a control gate 8. In a source and drain region of a hot electron type memory cell, write operation is conducted by storing information by applying a voltage of approximately 5 V to a drain and a voltage of appropriately 12 V to a control gate electrode and trapping hot electrons generated between the source and drain into the floating gate electrode. Meanwhile, erase operation is conducted by erasing information by applying a voltage of approximately 0 V and a voltage of approximately 12 V are applied to the control gate electrode and the source, respectively and absorbing electrons of the floating gate electrode. Therefore, the drain only consists of an N-type high concentration layer so as to easily generate hot electrons and the drain has a structure that a surface where the N-type high concentration layer contacts with the P well 3 is covered with a low concentration N-type layer so as not to generate hot electrons when a voltage of approximately 12 V is applied while erase operation is being conducted.
To form a source and a drain, high concentration N-type impurity atoms such as arsenic of a concentration of approximately 1.times.10.sup.16 atms/cm.sup.2 are injected only into the drain region 9-2 and the source region 9-1 of the memory cell portion and N-type impurity atoms such as phosphor having a concentration of approximately 1.times.10.sup.14 atms/cm.sup.2 are injected only into the source region 9-1 by ion implantation. Thermal treatment is conducted at 900 to 1000 .degree. C. to activate arsenic and phosphor atoms. During the thermal treatment, the diffusion speed of phosphor is higher than that of arsenic. Due to this, the high concentration source region 9-1 is covered with the low concentration N-type source region 9-3.
As shown in FIG. 4, a photoresist film 20 for forming gate electrodes on the peripheral circuit portion is patterned.
As shown in FIG. 5, using the photoresist film 20 as a mask, the polycrystalline silicon film 8 is selectively etched, to thereby form gate electrodes 8-1 and 8-2. Thereafter, the photoresist film 20 is removed.
As shown in FIG. 6, the memory cell portion A and the pMOS region C of the peripheral circuit portion are selectively covered with a photoresist 10-1. Low concentration N-type impurity atoms such as phosphor of a concentration of approximately 1.times.10.sup.13 to 5.times.10.sup.13 atms/cm.sup.2 are selectively injected into the nMOS region B of the peripheral circuit portion by ion implantation, thereby forming a low concentration source and drain region 11.
As shown in FIG. 7, the photoresist 10-1 is removed and a chemical vapor deposition oxide film is provided on the entire surface of the substrate. The entire surface of the substrate is anisotropically etched and oxide films 12 are formed only the side surfaces of the gate electrodes 6-1, 8a, 8-1 and 8-2 in a self-aligned manner, respectively. As shown in FIG. 8, portions other than the nMOS region B of the peripheral circuit portion are covered with a photoresist 10-2 and, for example, arsenic atoms of a concentration of 1.times.10.sup.15 to 1.times.10.sup.16 atms/cm.sup.2 are injected to thereby form a high concentration N-type source and drain region 13 in the nMOS region B of the peripheral circuit portion by ion implantation.
As shown in FIG. 9, boron atoms of a concentration of 1.times.10.sup.15 to 1.times.10.sup.16 atms/cm.sup.2 are injected into the pMOS region C of the peripheral circuit portion by ion implantation to thereby form a high concentration P-type source and drain region 14.
As shown in FIG. 10, an interlayer insulating film 15 such as a chemical vapor deposition oxide film is formed on the entire surface of the substrate. Opening portions are selectively provided in the source, drain and gate electrodes. Electrodes 16 of aluminum are selectively formed to cover the openings.
Since the conventional manufacturing method as mentioned above requires many manufacturing steps, it has disadvantages in that yield is lowered and manufacturing cost is increased.